1. Field of the Invention
The present invention relates to an electrostatic discharge protection circuit, and in particular to an electrostatic discharge protection circuit using a silicon controlled rectifier (SCR), which provides a low stray capacitance, a low trigger voltage, a wide operating voltage range, and a high electrostatic discharge (ESD) capability.
2. Background
To avoid the damage of integrated circuit (IC) suffered from electrostatic discharge (ESD) during the processes of construction, production and operation, therefore, ESD protection circuit must be added on all connected path of bonding wire to conduct ESD current.
In general, the protection circuit can be divided into: diode, metal oxide semiconductor (MOS) transistor, silicon controlled rectifier (SCR), etc. Wherein, the SCR exhibits the highest ESD capability under the same condition. However, the trigger voltage of conventional SCR was high to operate. For instance, Lateral SCR (LSCR) exhibits high ESD capability, but still did not be utilized frequently due to the high trigger voltage.
In order to decrease the trigger voltage, modified circuits of SCR were presented frequently. U.S. Pat. No. 4,896,243 discloses a modified lateral SCR (MLSCR). U.S. Pat. No. 4,939,616 discloses a low voltage triggering SCR (LVTSCR). Mergens propose a dual triggered SCR as reference “Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides,” in IEEE int. Electron Devices Meeting (IEDM) Tech. Dig., Washington, D.C., 2003, pp. 21.3.1-21.3.4.
In general, the total parasitic capacitance of connection pins between the circuit and ESD protection circuit must be smaller than 200 fF, or the high-speed transmission signal will be distorted by the delay of parasitic capacitances and cause poor circuit characteristics. For the design of high-speed transmission signal, MOS transistors are not suitable for ESD protection elements due to large parasitic capacitances. In addition, some researches proposed ESD protection elements based on small capacitances, such as H. Feng, K. Gong, and A. Z. Wang, “A comparison study of ESD protection for RFIC's: performance vs. parasitics,” in IEEE MTT-S int. Microwave Symp. Dig., Boston, Mass., 2000, pp. 143-146. C. Y. Lin and M. D. Ker, “Dual SCR with low-and-constant parasitic capacitance for ESD protection in 5-GHz RF intergrated circuits,” in IEEE in conf. Solid-State Integrated Circuit Tech. (ICSICT), Shanghai, 2010, pp. 707-709. M. H. Tsai, S. H. Hsu, F. L. Hsueh and C. P. Jou, “A multi-ESD-path low-noise amplifier with a 4.3-A TLP current level in 65-nm CMOS,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 12, pp. 4004-4011, 2010. M. P. J. Mergens, C. C. Russ, K. G. Verhaege, J. Armer, P. C. Jozwiak, R. P. Mohn, B. Keppens, and C. S. Trinh, “Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies,” IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 532-542, 2005. As above discussion, all these ESD protection circuits were formed based on SCR due to the high conducting capability of ESD current per unit area. Therefore, a compact layout size could be used to minimize parasitic capacitances with a basic ESD resistance.
FIG. 1 shows fail circuit diagram for TC 9003F31 RX pin receiving terminal. The ESD structure protects upper circuit by a diode with high P doping concentration/N-well (P+/NW), and protects lower circuit by a diode with high N doping concentration/P-well (N+/PW). When the pins are bombarded by an operation of ESD PS-mode (i.e. PS-mode means that VSS terminal connects with ground, a positive ESD voltage occurs at the pins and discharges the current of VSS terminal. At this moment, VDD terminal and the other pins are floating), in an ideal situation, the ESD current should flow through the upper P+/NW diode and be led to the ground by the power clamp circuit. In fact, when voltage (V1) is higher than the threshold voltage of M1 MOS transistor, and the M1 MOS transistor will break down. Therefore, the ESD current flows through the lower circuit and burns M1 MOS transistor. FIG. 2 is the measured curve of the transmission line pulse (TLP). Moreover, M1 MOS transistor is formed based on 55 nm process, which utilizes an operated voltage of 1.2V, leading to lower breakdown voltage of M1 MOS transistor.
In the ESD protection of the RF circuit, in addition to adjust the matching circuit (including the capacitor and the inductor), uses of diodes and SCR are better methods for ESD protection. However, diodes as the ESD protection circuit can merely provide forward ESD current protection, leading to diodes broken due to the voltage overflow. With the minimization of process, the breakdown voltage of the elements becomes small and the design difficulty thus increases.
Furthermore, the RX pin has a swing signal, which will cause a carrier effect. Therefore, the trigger voltage must be higher.
According to the disadvantage of the prior art, the inventors disclose an ESD protection circuit with a low capacitor, a wide operating voltage range, and a high ESD capability for resolving the problems about the ESD of the RX pins.